`include "define.v"
module wrtbak
(
input  clk,
input  rst_n,
input  [7:0] m_opcode,
input  [31:0] m_valM,
input  [31:0] m_valE,
input  [3:0] m_dstM,
input  [3:0] m_dstE,
input  [2:0] m_stat,   
input  W_stall,
input  W_bubble,
             
output [3:0] w_opcode,
output [31:0] w_valM,
output [31:0] w_valE,
output [3:0] w_dstM,
output [3:0] w_dstE,
output reg[2:0] w_stat  
);
ppregs_W U_ppregs_W
    (
	.clk(clk),
	.rst_n(rst_n),
	.W_stall(W_stall),
    .W_bubble(W_bubble),
	.opcode_i(m_opcode),
	.dstE_i(m_dstE),
	.dstM_i(m_dstM),
	.valE_i(m_valE),
	.valM_i(m_valM),
	
	.opcode_o(w_opcode),
	.dstE_o(w_dstE),
	.dstM_o(w_dstM),
	.valM_o(w_valM),
	.valE_o(w_valE)
	    );
always @ (posedge clk or posedge rst_n)
begin
	if(~rst_n)
	begin
	    w_stat<=`ST_AOK;
	end
	else
	begin
	    if(W_stall)
		w_stat<=w_stat;
	    else if(W_bubble)
		w_stat<=`ST_AOK;
	    else if(w_opcode=={`NORM_INS,`HALT})
		w_stat<=`ST_HLT;
	    else
		w_stat<=m_stat;
	end
end
endmodule
